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?2003 fairchild semiconductor corporation rev. a, june 2003 fqp9n50c/fqpf9n50c qfet tm fqp9n50c/fqpf9n50c 500v n-channel mosfet general description these n-channel enhancement mode power field effect transistors are produced using fairchild?s proprietary, planar stripe, dmos technology. this advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. these devices are well suited for high efficiency switched mode power supplies, active power factor correction, electronic lamp ballasts based on half bridge topology. features 9 a, 500v, r ds(on) = 0.8 ? @v gs = 10 v low gate charge ( typical 28 nc) low crss ( typical 24 pf) fast switching 100% avalanche tested improved dv/dt capability absolute maximum ratings t c = 25c unless otherwise noted * drain current limited by maximum junction temperature thermal characteristics symbol parameter fqp9n50c fqpf9n50c units v dss drain-source voltage 500 v i d drain current - continuous (t c = 25c) 99 *a - continuous (t c = 100c) 5.4 5.4 * a i dm drain current - pulsed (note 1) 36 36 * a v gss gate-source voltage 30 v e as single pulsed avalanche energy (note 2) 360 mj i ar avalanche current (note 1) 9a e ar repetitive avalanche energy (note 1) 13.5 mj dv/dt peak diode recovery dv/dt (note 3) 4.5 v/ns p d power dissipation (t c = 25c) 135 44 w - derate above 25c 1.07 0.35 w/c t j , t stg operating and storage temperature range -55 to +150 c t l maximum lead temperature for soldering purposes, 1/8 " from case for 5 seconds 300 c symbol parameter fqp9n50c fqpf9n50c units r jc thermal resistance, junction-to-case 0.93 2.86 c / w r cs thermal resistance, case-to-sink typ. 0.5 -- c / w r ja thermal resistance, junction-to-ambient 62.5 62.5 c / w to-220 fqp series g s d to-220f fqpf series g s d ! ! ! ! ! ! ! ! ! ! ! ! ? ? ? ? ! ! ! ! ! ! ! ! ! ! ! ! ? ? ? ? s d g
rev. a, june 2003 fqp9n50c/fqpf9n50c ?2003 fairchild semiconductor corporation electrical characteristics t c = 25c unless otherwise noted notes: 1. repetitive rating : pulse width limited by maximum junction temperature 2. l = 8 mh, i as = 9a, v dd = 50v, r g = 25 ?, starting t j = 25c 3. i sd 9a, di/dt 200a/ s, v dd bv dss, starting t j = 25c 4. pulse test : pulse width 300 s, duty cycle 2% 5. essentially independent of operating temperature symbol parameter test conditions min typ max units off characteristics bv dss drain-source breakdown voltage v gs = 0 v, i d = 250 a 500 -- -- v ? bv dss / ? t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25c -- 0.57 -- v/c i dss zero gate voltage drain current v ds = 500 v, v gs = 0 v -- -- 1 a v ds = 400 v, t c = 125c -- -- 10 a i gssf gate-body leakage current, forward v gs = 30 v, v ds = 0 v -- -- 100 na i gssr gate-body leakage current, reverse v gs = -30 v, v ds = 0 v -- -- -100 na on characteristics v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 2.0 -- 4.0 v r ds(on) static drain-source on-resistance v gs = 10 v, i d = 4.5 a -- 0.65 0.8 ? g fs forward transconductance v ds = 40 v, i d = 4.5 a (note 4) -- 6.5 -- s dynamic characteristics c iss input capacitance v ds = 25 v, v gs = 0 v, f = 1.0 mhz -- 790 1030 pf c oss output capacitance -- 130 170 pf c rss reverse transfer capacitance -- 24 30 pf switching characteristics t d(on) turn-on delay time v dd = 250 v, i d = 9 a, r g = 25 ? (note 4, 5) -- 18 45 ns t r turn-on rise time -- 65 140 ns t d(off) turn-off delay time -- 93 195 ns t f turn-off fall time -- 64 125 ns q g total gate charge v ds = 400 v, i d = 9 a, v gs = 10 v (note 4, 5) -- 28 35 nc q gs gate-source charge -- 4 -- nc q gd gate-drain charge -- 15 -- nc drain-source diode characteristics and maximum ratings i s maximum continuous drain-source diode forward current -- -- 9 a i sm maximum pulsed drain-source diode forward current -- -- 36 a v sd drain-source diode forward voltage v gs = 0 v, i s = 9 a -- -- 1.4 v t rr reverse recovery time v gs = 0 v, i s = 9 a, di f / dt = 100 a/ s (note 4) -- 335 -- ns q rr reverse recovery charge -- 2.95 -- c
rev. a, june 2003 fqp9n50c/fqpf9n50c ?2003 fairchild semiconductor corporation 0 5 10 15 20 25 30 0 2 4 6 8 10 12 v ds = 250v v ds = 100v v ds = 400v note : i d = 9a v gs , gate-source voltage [v] q g , total gate charge [nc] 0.2 0.4 0.6 0.8 1.0 1.2 1.4 10 -1 10 0 10 1 150 notes : 1. v gs = 0v 2. 250 s pulse test 25 i dr , reverse drain current [a] v sd , source-drain voltage [v] 0 5 10 15 20 25 0.5 1.0 1.5 2.0 v gs = 20v v gs = 10v note : t j = 25 r ds(on) [ ], drain-source on-resistance i d , drain current [a] typical characteristics figure 5. capacitance characteristics figure 6. gate charge characteristics figure 3. on-resistance variation vs drain current and gate voltage figure 4. body diode forward voltage variation with source current and temperature figure 2. transfer characteristics figure 1. on-region characteristics 10 -1 10 0 10 1 10 -1 10 0 10 1 v gs top : 15.0 v 10.0 v 8.0 v 7.0 v 6.0 v 5.5 v 5.0 v bottom : 4.5 v notes : 1. 250 s pulse test 2. t c = 25 i d , drain current [a] v ds , drain-source voltage [v] 246810 10 -1 10 0 10 1 150 o c 25 o c -55 o c notes : 1. v ds = 40v 2. 250 s pulse test i d , drain current [a] v gs , gate-source voltage [v] 10 -1 10 0 10 1 0 400 800 1200 1600 2000 c iss = c gs + c gd (c ds = shorted) c oss = c ds + c gd c rss = c gd notes ; 1. v gs = 0 v 2. f = 1 mhz c rss c oss c iss capacitance [pf] v ds , drain-source voltage [v]
rev. a, june 2003 fqp9n50c/fqpf9n50c ?2003 fairchild semiconductor corporation 10 0 10 1 10 2 10 3 10 -2 10 -1 10 0 10 1 10 2 100 ms 10 s dc 10 ms 1 ms 100 s operation in this area is limited by r ds(on) notes : 1. t c = 25 o c 2. t j = 150 o c 3. single pulse i d , drain current [a] v ds , drain-source voltage [v] 10 0 10 1 10 2 10 3 10 -2 10 -1 10 0 10 1 10 2 100 ms 10 s dc 10 ms 1 ms 100 s operation in this area is limited by r ds(on) notes : 1. t c = 25 o c 2. t j = 150 o c 3. single pulse i d , drain current [a] v ds , drain-source voltage [v] typical characteristics (continued) figure 9-1. maximum safe operating area for fqp9n50c figure 10. maximum drain current vs case temperature figure 7. breakdown voltage variation vs temperature figure 8. on-resistance variation vs temperature figure 9-2. maximum safe operating area for fqpf9n50c -100 -50 0 50 100 150 200 0.8 0.9 1.0 1.1 1.2 notes : 1. v gs = 0 v 2. i d = 250 a bv dss , (normalized) drain-source breakdown voltage t j , junction temperature [ o c] -100 -50 0 50 100 150 200 0.0 0.5 1.0 1.5 2.0 2.5 3.0 notes : 1. v gs = 10 v 2. i d = 4.5 a r ds(on) , (normalized) drain-source on-resistance t j , junction temperature [ o c] 25 50 75 100 125 150 0 2 4 6 8 10 i d , drain current [a] t c , case temperature [ ]
rev. a, june 2003 fqp9n50c/fqpf9n50c ?2003 fairchild semiconductor corporation 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 -2 10 -1 10 0 notes : 1. z jc (t) = 2.86 /w m a x. 2. d u ty f a c to r, d = t 1 /t 2 3. t jm - t c = p dm * z jc (t) single pulse d=0.5 0.02 0.2 0.05 0.1 0.01 z jc (t), therm al response t 1 , square w ave pulse duration [sec] 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 -2 10 -1 10 0 notes : 1. z jc (t) = 0.93 /w m a x. 2. d u ty f a c to r, d = t 1 /t 2 3. t jm - t c = p dm * z jc (t) s in g le pu ls e d=0.5 0.02 0.2 0.05 0.1 0.01 z jc (t), therm al response t 1 , square w ave pulse duration [sec] typical characteristics (continued) figure 11-1. transient thermal response curve for fqp9n50c figure 11-2. transient thermal response curve for fqpf9n50c t 1 p dm t 2 t 1 p dm t 2
rev. a, june 2003 fqp9n50c/fqpf9n50c ?2003 fairchild semiconductor corporation gate charge test circuit & waveform resistive switching test circuit & waveforms unclamped inductive switching test circuit & waveforms charge v gs 10v q g q gs q gd 3ma v gs dut v ds 300nf 50k 200nf 12v same type as dut charge v gs 10v q g q gs q gd 3ma v gs dut v ds 300nf 50k 200nf 12v same type as dut v gs v ds 10% 90% t d(on) t r t on t off t d(off) t f v dd 10v v ds r l dut r g v gs v gs v ds 10% 90% t d(on) t r t on t off t d(off) t f v dd 10v v ds r l dut r g v gs e as =li as 2 ---- 2 1 -------------------- bv dss -v dd bv dss v dd v ds bv dss t p v dd i as v ds (t) i d (t) time 10v dut r g l i d t p e as =li as 2 ---- 2 1 e as =li as 2 ---- 2 1 ---- 2 1 -------------------- bv dss -v dd bv dss v dd v ds bv dss t p v dd i as v ds (t) i d (t) time 10v dut r g l l i d i d t p
rev. a, june 2003 fqp9n50c/fqpf9n50c ?2003 fairchild semiconductor corporation peak diode recovery dv/dt test circuit & waveforms dut v ds + _ driver r g same type as dut v gs dv/dt controlled by r g i sd controlled by pulse period v dd l i sd 10v v gs ( driver ) i sd ( dut ) v ds ( dut ) v dd body diode forward voltage drop v sd i fm , body diode forward current body diode reverse current i rm body diode recovery dv/dt di/dt d = gate pulse width gate pulse period -------------------------- dut v ds + _ driver r g same type as dut v gs dv/dt controlled by r g i sd controlled by pulse period v dd l l i sd 10v v gs ( driver ) i sd ( dut ) v ds ( dut ) v dd body diode forward voltage drop v sd i fm , body diode forward current body diode reverse current i rm body diode recovery dv/dt di/dt d = gate pulse width gate pulse period -------------------------- d = gate pulse width gate pulse period --------------------------
rev. a, june 2003 fqp9n50c/fqpf9n50c ?2003 fairchild semiconductor corporation package dimensions 4.50 0.20 9.90 0.20 1.52 0.10 0.80 0.10 2.40 0.20 10.00 0.20 1.27 0.10 ?.60 0.10 (8.70) 2.80 0.10 15.90 0.20 10.08 0.30 18.95max. (1.70) (3.70) (3.00) (1.46) (1.00) (45 ) 9.20 0.20 13.08 0.20 1.30 0.10 1.30 +0.10 ?.05 0.50 +0.10 ?.05 2.54typ [2.54 0.20 ] 2.54typ [2.54 0.20 ] to-220 dimensions in millimeters
rev. a, june 2003 fqp9n50c/fqpf9n50c ?2003 fairchild semiconductor corporation package dimensions (continued) (7.00) (0.70) max1.47 (30 ) #1 3.30 0.10 15.80 0.20 15.87 0.20 6.68 0.20 9.75 0.30 4.70 0.20 10.16 0.20 (1.00x45 ) 2.54 0.20 0.80 0.10 9.40 0.20 2.76 0.20 0.35 0.10 3.18 0.10 2.54typ [2.54 0.20 ] 2.54typ [2.54 0.20 ] 0.50 +0.10 0.05 to-220f dimensions in millimeters
?2003 fairchild semiconductor corporation disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information formative or in design this datasheet contains the design specifications for product development. specifications may change in any manner without notice. preliminary first production this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. no identification needed full production this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. obsolete not in production this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. rev. i2 trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. fact? fact quiet series? fast ? fastr? frfet? globaloptoisolator? gto? hisec? i 2 c? implieddisconnect? isoplanar? littlefet? microfet? micropak? microwire? msx? msxpro? ocx? ocxpro? optologic ? optoplanar? pacman? pop? power247? powertrench ? qfet? qs? qt optoelectronics? quiet series? rapidconfigure? rapidconnect? silent switcher ? smart start? spm? stealth? supersot?-3 supersot?-6 supersot?-8 syncfet? tinylogic ? trutranslation? uhc? ultrafet ? vcx? acex? activearray? bottomless? coolfet? crossvolt ? dome? ecospark? e 2 cmos? ensigna? across the board. around the world.? the power franchise? programmable active droop?
careers | sitema go datasheets, samples, buy technical information applications design center support company investors my f a home >> find products >> product status/pricing/packaging fqpf9n50c 500v n-channel advance q-fet c-series general description back to top features back to top contents ? general description ? features ? product status/pricing/packaging ? order samples ? models ? qualification support these n-channel enhancement mode pow er field effect transistors are produced using fairchild?s proprietary, planar stripe, dmos technology. this advanced technology has been especially tailored to minimize on-state resistance, provide superior switchin g performance, and withstand high energy pulse in the avalanche and commutation mode. these devices are well suited for high effi ciency switched mo de power supplies, active power facto r correction, electronic lamp ballasts based on half bridge topology. z 9a, 500v { r ds(on) = 0.8 ? @ v gs = 10v z low gate charge ( typical 28 nc) z low crss ( typical 24 pf) z fast switching z 100% avalanche tested z improved dv/dt capability datasheet download this datasheet e - mail this datasheet this page print version related links request samples how to order products product change notices (pcns) support sales support quality and reliability design cente r pa g e 1 of 3 product folder - fairchild p/n fqpf9n50c - 500v n-cha nnel advance q-fet c-series 17-au g -2007 mhtml:file://c:\temp\fqpf9n50ct.mht
back to top models back to top qualification support click on a product for detailed qualification data product product status pb-free status pricing* package type leads packing method package marking convention** fqpf9n50c full production $1.10 to - 220f 3 rail line 1: $y (fairchild logo) & z (asm. plant code) & 4 (4-digit date code) line 2: fqpf line 3: 9n50c fqpf9n50ct full production $1.14 to - 220f 3 rail line 1: $y (fairchild logo) & z (asm. plant code) & 4 (4-digit date code) FQPF9N50CYDTU preliminary $1.20 to-220f 3 rail line 1: $y (fairchild logo) & z (asm. plant code) &e& 3 (3-digit date code) line 2: fqpf line 3: 9n50c * fairchild 1,000 piece budgetary pricing ** a sample button will appear if the part is available through fa irchild's on-line samples program. if there is no sample butt on, please contact a fairchild distributo r to obtain samples indicates product with pb -free second-level interconne ct. for more information click here. package marking information for product fqpf9n50c is available. click here for more information . package & leads condition temperature range vcc range software version revision date pspice to-220f-3 electrical/thermal -55c to 150c 0v to 50v orcad 10.3 jul 27, 2007 product fqpf9n50c fqpf9n50ct FQPF9N50CYDTU pa g e 2 of 3 product folder - fairchild p/n fqpf9n50c - 500v n-cha nnel advance q-fet c-series 17-au g -2007 mhtml:file://c:\temp\fqpf9n50ct.mht
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